User Tools

Site Tools


vivado_2018.3_zedboard

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
vivado_2018.3_zedboard [2019/05/17 16:37]
rpjday [Overview]
vivado_2018.3_zedboard [2019/05/17 16:42] (current)
rpjday [Steps]
Line 20: Line 20:
     * "ZYNQ7 Processing System"​     * "ZYNQ7 Processing System"​
   * Validate, error with M_AXI_GP0_ACLK   * Validate, error with M_AXI_GP0_ACLK
-  * Double click on design block graphic ​(menu entry?):+  * Double click on design block graphic:
     * PS-PL Configuration     * PS-PL Configuration
       * AXI Non Secure Enablement       * AXI Non Secure Enablement
Line 26: Line 26:
           * M AXI GP0 Interface (uncheck)           * M AXI GP0 Interface (uncheck)
   * Validate again (should pass)   * Validate again (should pass)
-  * Generate Block Design 
   * BLOCK DESIGN   * BLOCK DESIGN
     * Right click     * Right click
       * "​Create HDL wrapper"​       * "​Create HDL wrapper"​
 +  * Generate block design
   * Run Synthesis   * Run Synthesis
   * Run implementation   * Run implementation
   * Generate bitstream   * Generate bitstream
   * Export hardware (include bitstream?)   * Export hardware (include bitstream?)
vivado_2018.3_zedboard.txt ยท Last modified: 2019/05/17 16:42 by rpjday