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vivado_2018.3_zedboard [2019/05/17 11:59]
rpjday [Steps]
vivado_2018.3_zedboard [2019/05/17 16:42] (current)
rpjday [Steps]
Line 1: Line 1:
 ===== Overview ===== ===== Overview =====
  
-Steps in building ​the exporting the output for Zynq Zedboard from Vivado 2018.3.+Steps in building/exporting the output for Zynq Zedboard from Vivado 2018.3.
  
-Links: 
- 
-  * [[https://​forums.xilinx.com/​t5/​Embedded-Development-Tools/​Vivado-exporting-hardware-issue/​td-p/​923199]] 
  
 ===== Directory setup ===== ===== Directory setup =====
  
 <​code>​ <​code>​
-$ mkdir /tmp/projects && cd /tmp/​projects+$ mkdir ~/xilinx/vivado_projects/zedboard_project
 </​code>​ </​code>​
  
Line 19: Line 16:
     * "Do not specify sources at this time"     * "Do not specify sources at this time"
     * Select Zedboard part, Finish     * Select Zedboard part, Finish
-  * Create Block Design+  * Create Block Design ​(take all defaults)
     * Empty design, "​+"​     * Empty design, "​+"​
     * "ZYNQ7 Processing System"​     * "ZYNQ7 Processing System"​
   * Validate, error with M_AXI_GP0_ACLK   * Validate, error with M_AXI_GP0_ACLK
-  * Double click on design block graphic ​(menu entry?):+  * Double click on design block graphic:
     * PS-PL Configuration     * PS-PL Configuration
       * AXI Non Secure Enablement       * AXI Non Secure Enablement
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           * M AXI GP0 Interface (uncheck)           * M AXI GP0 Interface (uncheck)
   * Validate again (should pass)   * Validate again (should pass)
-  * File -> Export -> Block Design (Generate Block Design?) 
   * BLOCK DESIGN   * BLOCK DESIGN
-    * Sources +    * Right click 
-      * Right click on design, ​Create HDL Wrapper (why?)+      * "Create HDL wrapper"​ 
 +  * Generate block design
   * Run Synthesis   * Run Synthesis
   * Run implementation   * Run implementation
-  * (Finally) Export Hardware (include bitstream?) 
   * Generate bitstream   * Generate bitstream
 +  * Export hardware (include bitstream?)
vivado_2018.3_zedboard.1558094397.txt.gz · Last modified: 2019/05/17 11:59 by rpjday