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risc-v [2022/03/01 11:12]
rpjday [git/build/platform/generic/firmware]
risc-v [2022/03/01 14:09] (current)
rpjday [meta-riscv layer [abbreviated]]
Line 27: Line 27:
         * [[https://​git.openembedded.org/​openembedded-core/​tree/​meta/​recipes-bsp/​opensbi/​opensbi_1.0.bb|opensbi_1.0.bb]]         * [[https://​git.openembedded.org/​openembedded-core/​tree/​meta/​recipes-bsp/​opensbi/​opensbi_1.0.bb|opensbi_1.0.bb]]
         * [[https://​git.openembedded.org/​openembedded-core/​tree/​meta/​recipes-bsp/​opensbi/​opensbi-payloads.inc|opensbi-payloads.inc]]         * [[https://​git.openembedded.org/​openembedded-core/​tree/​meta/​recipes-bsp/​opensbi/​opensbi-payloads.inc|opensbi-payloads.inc]]
 +      * [[https://​git.openembedded.org/​openembedded-core/​tree/​meta/​recipes-bsp/​u-boot|u-boot/​]]
 +        * [[https://​git.openembedded.org/​openembedded-core/​tree/​meta/​recipes-bsp/​u-boot/​u-boot-common.inc|u-boot-common.inc]]
 +        * [[https://​cgit.openembedded.org/​openembedded-core/​tree/​meta/​recipes-bsp/​u-boot/​u-boot.inc|u-boot.inc]]
 +        * [[https://​cgit.openembedded.org/​openembedded-core/​tree/​meta/​recipes-bsp/​u-boot/​u-boot_2022.01.bb|u-boot_2022.01.bb]]
  
  
-== meta-riscv layer [abbreviated]+== meta-riscv layer [abbreviated, unnecessary for QEMU]
  
   * [[https://​github.com/​riscv/​meta-riscv|meta-riscv/​]]   * [[https://​github.com/​riscv/​meta-riscv|meta-riscv/​]]
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     * [[https://​github.com/​riscv/​meta-riscv/​tree/​master/​recipes-bsp/​u-boot|U-Boot stuff]]     * [[https://​github.com/​riscv/​meta-riscv/​tree/​master/​recipes-bsp/​u-boot|U-Boot stuff]]
     * [[https://​github.com/​riscv/​meta-riscv/​tree/​master/​recipes-kernel/​|recipes-kernel/​]]     * [[https://​github.com/​riscv/​meta-riscv/​tree/​master/​recipes-kernel/​|recipes-kernel/​]]
-      * [[https://​github.com/​riscv/​meta-riscv/​tree/​master/​recipes-kernel/​firmware|firmware/​]] 
       * [[https://​github.com/​riscv/​meta-riscv/​tree/​master/​recipes-kernel/​linux|linux/​]]       * [[https://​github.com/​riscv/​meta-riscv/​tree/​master/​recipes-kernel/​linux|linux/​]]
  
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 </​code>​ </​code>​
  
-Why create a kernel containing-payload if you don't use it?+Why create a kernel containing-payload if you don't use it? Also, appears that the serial console is ''​ttyS0'',​ and you can drop the ''​console=hvc0 earlycon=sbi''​ stuff, still works.
  
 == tmp/​deploy/​images/​qemuriscv64 == tmp/​deploy/​images/​qemuriscv64
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 -rwxr-xr-x. 2 rpjday rpjday 2713192 Mar  1 06:10 fw_payload.bin -rwxr-xr-x. 2 rpjday rpjday 2713192 Mar  1 06:10 fw_payload.bin
 -rwxr-xr-x. 2 rpjday rpjday 1554336 Mar  1 06:10 fw_payload.elf -rwxr-xr-x. 2 rpjday rpjday 1554336 Mar  1 06:10 fw_payload.elf
-</core>+</code> 
 == log.do_compile == log.do_compile
  
risc-v.1646133147.txt.gz · Last modified: 2022/03/01 11:12 by rpjday