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Overview of MAC/PHY/PCS/PMA/PMD. Hierarchy:

• Data link layer
  • LLC
  • MAC (FLGA core)
• Reconciliation
• PHY (FPGA core)
  • PCS (Physical Coding Sublayer)
  • PMA (Physical Medium Attachment)
  • PMD (Physical Medium Dependent)
  • [AUTONEG]
• MDI (Medium Dependent Interface)
• Medium

FPGA breakdown (communicates via XGMII) – “MAC block is today typically integrated with the PHY within the same device package”:

• MAC core
• 10G Ethernet PCS/PMA core

“The LogiCORE™ IP 10G Ethernet Physical Coding Sublayer/Physical Medium Attachment (PCS/PMA) core forms a seamless interface between the Xilinx 10G Ethernet Media Access Controller (MAC) core and a 10 Gb/s-capable PHY, enabling the design of high-speed Ethernet systems and subsystems.”

“The Management Data Input/Output (MDIO) serial bus is a subset of the MII that is used to transfer management information between MAC and PHY. At power up, using autonegotiation, the PHY usually adapts to whatever it is connected to unless settings are altered via the MDIO interface.”

Links:

• !000BASE-T1
• IEEE P802.3ba
• Xilinx 10G Ethernet PCS/PMA v6.0
• Demystifying the MAC, PCS and PHY & how to measure their latency

Possible vendor offerings:

• link traffic counters
• RX (and TX) timestamping
• support for Ethernet flow control
• a dual-clock FIFO on the receive side
• IEEE 1588 (PTP) support
• support for options not strictly in conformance of the 10GbE spec such as shrinking the Ethernet preamble and/or interpacket gap to reduce latency between MAC and PHYs offering this support

• Physical: The physical medium is quite likely to either be a fibre patchcord or a twinaxial copper cable.
• PMD: This is plugged into a transceiver which implements the PMD, converting whatever physical medium is used; light or electrons, into a stream of electrons matching a defined interface talking to the PMA.
• PMA: The PMA is part of an FPGA chip and does a number of things. It works out where each bit begins and ends in the stream and recovers the clock from the stream. It then deserialises the incoming stream at 10.3125 Gbps into typically a 32 or 64 bit bus clocked at ~322 Mhz or ~161 Mhz which is passed to the PCS.
• PCS: The PCS first synchronises with the stream by identifying special symbols sent periodically in the stream to indicate the start of a line-encoded block. It then descrambles the blocks which have been scrambled using a polynomial scrambler designed to prevent DC bias (too many zeros or ones in succession that would cause a loss of lock by the PMA and PCS or too many ones in succession that would cause bit errors) and passes the descrambled stream to the MAC. Some models of FPGA have hard IP implementations of this layer.
• MAC: The MAC converts the decoded stream into Ethernet frames which it passes to the FPGA application. It also flags errors in the stream and maintains statistics. A PTP-aware MAC also timestamps Ethernet frames for PTP clock synchronisation

• receive/transmit normal frames
• half-duplex retransmission and backoff functions
• append/check FCS (frame check sequence)
• interframe gap enforcement
• discard malformed frames
• prepend(tx)/remove(rx) preamble, SFD (start frame delimiter), and padding
• half-duplex compatibility: append(tx)/remove(rx) MAC address

• PCS/PMA management registers with optional MDIO interface

“This sublayer determines when a functional link has been established, provides rate difference compensation, and performs coding such as 64b/66b encoding and scrambling/descrambling.”