Steps in building/exporting the output for Zynq Zedboard from Vivado 2018.3.

$ mkdir ~/xilinx/projects/vpjs/[zed_top/zedboard/]

• Select Zedboard (create subdirectory)
• RTL project
  • “Do not specify sources at this time”
• Select Zedboard part, Finish

End result:

.
├── vivado.jou
├── vivado.log
├── vivado_pid5494.str
└── zedboard
    ├── zedboard.cache
    │   └── wt
    │       └── project.wpc
    ├── zedboard.hw
    │   └── zedboard.lpr
    ├── zedboard.ip_user_files
    ├── zedboard.sim
    └── zedboard.xpr

• Create Block Design (take all defaults)
  • Empty design, “+”
  • “ZYNQ7 Processing System”

End result:

.
├── vivado.jou
├── vivado.log
├── vivado_pid5494.str
└── zedboard
    ├── zedboard.cache
    │   └── wt
    │       └── project.wpc
    ├── zedboard.hw
    │   └── zedboard.lpr
    ├── zedboard.ip_user_files
    ├── zedboard.sim
    ├── zedboard.srcs
    │   └── sources_1
    │       └── bd
    │           └── design_1
    │               └── design_1.bd
    └── zedboard.xpr

design_1.bd:

{
  "design": {
    "design_info": {
      "boundary_crc": "0x0",
      "name": "design_1",
      "synth_flow_mode": "Hierarchical",
      "tool_version": "2018.3"
    },
    "design_tree": {}
  }
}

• Validate, error with M_AXI_GP0_ACLK
• Double click on design block graphic:
  • PS-PL Configuration
    • AXI Non Secure Enablement
      • GP Master AXI Interface
        • M AXI GP0 Interface (uncheck)
• Validate again (should pass)
• BLOCK DESIGN
  • Right click
    • “Create HDL wrapper”
• Generate block design
• Run Synthesis
• Run implementation
• Generate bitstream
• Export hardware (include bitstream?)