Steps in building the exporting the output for Zynq Zedboard from Vivado 2018.3.

$ mkdir ~/xilinx/vivado_projects/zedboard_project

• Select Zedboard (create subdirectory)
  • RTL project
  • “Do not specify sources at this time”
  • Select Zedboard part, Finish
• Create Block Design (take all defaults)
  • Empty design, “+”
  • “ZYNQ7 Processing System”
• Validate, error with M_AXI_GP0_ACLK
• Double click on design block graphic (menu entry?):
  • PS-PL Configuration
    • AXI Non Secure Enablement
      • GP Master AXI Interface
        • M AXI GP0 Interface (uncheck)
• Validate again (should pass)
• Generate Block Design
• BLOCK DESIGN
  • Right click
    • “Create HDL wrapper”
• Run Synthesis
• Run implementation
• Generate bitstream
• Export hardware (include bitstream?)