Overview of MAC/PHY/PCS/PMA/PMD. Hierarchy:

• Data link layer
  • LLC
  • MAC
• Reconciliation
• PHY
  • PCS (Physical Coding Sublayer)
  • PMA (Physical Medium Attachment)
  • PMD (Physical Medium Dependent)
• MDI (Medium Dependent Interface)
• Medium

FPGA breakdown (communicates via XGMII) – “MAC block is today typically integrated with the PHY within the same device package”:

• MAC core
• 10G Ethernet PCS/PMA core

“The LogiCORE™ IP 10G Ethernet Physical Coding Sublayer/Physical Medium Attachment (PCS/PMA) core forms a seamless interface between the Xilinx 10G Ethernet Media Access Controller (MAC) core and a 10 Gb/s-capable PHY, enabling the design of high-speed Ethernet systems and subsystems.”

“The Management Data Input/Output (MDIO) serial bus is a subset of the MII that is used to transfer management information between MAC and PHY. At power up, using autonegotiation, the PHY usually adapts to whatever it is connected to unless settings are altered via the MDIO interface.”

Links:

• !000BASE-T1
• IEEE P802.3ba
• Xilinx 10G Ethernet PCS/PMA v6.0
• Demystifying the MAC, PCS and PHY & how to measure their latency

Possible vendor offerings:

• link traffic counters
• RX (and TX) timestamping
• support for Ethernet flow control
• a dual-clock FIFO on the receive side
• IEEE 1588 (PTP) support
• support for options not strictly in conformance of the 10GbE spec such as shrinking the Ethernet preamble and/or interpacket gap to reduce latency between MAC and PHYs offering this support