In-kernel structures for MII and MDIO.

#include <linux/types.h>
#include <linux/ethtool.h>

/* Generic MII registers. */
#define MII_BMCR                0x00    /* Basic mode control register */
#define MII_BMSR                0x01    /* Basic mode status register  */
#define MII_PHYSID1             0x02    /* PHYS ID 1                   */
#define MII_PHYSID2             0x03    /* PHYS ID 2                   */

#include <linux/types.h>
#include <linux/mii.h>

/* MDIO Manageable Devices (MMDs). */
#define MDIO_MMD_PMAPMD         1       /* Physical Medium Attachment/
                                         * Physical Medium Dependent */
#define MDIO_MMD_WIS            2       /* WAN Interface Sublayer */
#define MDIO_MMD_PCS            3       /* Physical Coding Sublayer */
#define MDIO_MMD_PHYXS          4       /* PHY Extender Sublayer */
#define MDIO_MMD_DTEXS          5       /* DTE Extender Sublayer */
#define MDIO_MMD_TC             6       /* Transmission Convergence */
#define MDIO_MMD_AN             7       /* Auto-Negotiation */
#define MDIO_MMD_C22EXT         29      /* Clause 22 extension */
#define MDIO_MMD_VEND1          30      /* Vendor specific 1 */
#define MDIO_MMD_VEND2          31      /* Vendor specific 2 */

/* Generic MDIO registers. */
#define MDIO_CTRL1              MII_BMCR
#define MDIO_STAT1              MII_BMSR
#define MDIO_DEVID1             MII_PHYSID1
#define MDIO_DEVID2             MII_PHYSID2
#define MDIO_SPEED              4       /* Speed ability */
#define MDIO_DEVS1              5       /* Devices in package */
#define MDIO_DEVS2              6
#define MDIO_CTRL2              7       /* 10G control 2 */
#define MDIO_STAT2              8       /* 10G status 2 */
#define MDIO_PMA_TXDIS          9       /* 10G PMA/PMD transmit disable */
#define MDIO_PMA_RXDET          10      /* 10G PMA/PMD receive signal detect */
#define MDIO_PMA_EXTABLE        11      /* 10G PMA/PMD extended ability */
#define MDIO_PKGID1             14      /* Package identifier */
#define MDIO_PKGID2             15

#define MDIO_AN_ADVERTISE       16      /* AN advertising (base page) */
#define MDIO_AN_LPA             19      /* AN LP abilities (base page) */

#define MDIO_PCS_EEE_ABLE       20      /* EEE Capability register */
#define MDIO_PCS_EEE_WK_ERR     22      /* EEE wake error counter */

#define MDIO_PHYXS_LNSTAT       24      /* PHY XGXS lane state */

#define MDIO_AN_EEE_ADV         60      /* EEE advertisement */
#define MDIO_AN_EEE_LPABLE      61      /* EEE link partner ability */

/* Media-dependent registers. */
#define MDIO_PMA_10GBT_SWAPPOL  130     /* 10GBASE-T pair swap & polarity */
#define MDIO_PMA_10GBT_TXPWR    131     /* 10GBASE-T TX power control */
#define MDIO_PMA_10GBT_SNR      133     /* 10GBASE-T SNR margin, lane A.
                                         * Lanes B-D are numbered 134-136. */
#define MDIO_PMA_10GBR_FECABLE  170     /* 10GBASE-R FEC ability */
#define MDIO_PCS_10GBX_STAT1    24      /* 10GBASE-X PCS status 1 */
#define MDIO_PCS_10GBRT_STAT1   32      /* 10GBASE-R/-T PCS status 1 */
#define MDIO_PCS_10GBRT_STAT2   33      /* 10GBASE-R/-T PCS status 2 */
#define MDIO_AN_10GBT_CTRL      32      /* 10GBASE-T auto-negotiation control */
#define MDIO_AN_10GBT_STAT      33      /* 10GBASE-T auto-negotiation status */