===== Overview =====
Steps in building/exporting the output for Zynq Zedboard from Vivado 2018.3.
===== Directory setup =====
$ mkdir ~/xilinx/projects/vpjs/[zed_top/zedboard/]
===== Vivado steps =====
==== Create new project ====
* Select Zedboard (create subdirectory)
* RTL project
* "Do not specify sources at this time"
* Select Zedboard part, Finish
End result:
.
├── vivado.jou
├── vivado.log
├── vivado_pid5494.str
└── zedboard
├── zedboard.cache
│ └── wt
│ └── project.wpc
├── zedboard.hw
│ └── zedboard.lpr
├── zedboard.ip_user_files
├── zedboard.sim
└── zedboard.xpr
==== Create block design ====
* Create Block Design (take all defaults)
* Empty design, "+"
* "ZYNQ7 Processing System"
End result:
.
├── vivado.jou
├── vivado.log
├── vivado_pid5494.str
└── zedboard
├── zedboard.cache
│ └── wt
│ └── project.wpc
├── zedboard.hw
│ └── zedboard.lpr
├── zedboard.ip_user_files
├── zedboard.sim
├── zedboard.srcs
│ └── sources_1
│ └── bd
│ └── design_1
│ └── design_1.bd
└── zedboard.xpr
''design_1.bd'':
{
"design": {
"design_info": {
"boundary_crc": "0x0",
"name": "design_1",
"synth_flow_mode": "Hierarchical",
"tool_version": "2018.3"
},
"design_tree": {}
}
}
==== Validation ====
* Validate, error with M_AXI_GP0_ACLK
* Double click on design block graphic:
* PS-PL Configuration
* AXI Non Secure Enablement
* GP Master AXI Interface
* M AXI GP0 Interface (uncheck)
* Validate again (should pass)
==== Create HDL wrapper ====
* BLOCK DESIGN; design_1; Sources; right-click
* "Create HDL wrapper", let Vivado manage wrapper
Primary output:
$ tree zedboard.srcs
zedboard.srcs
└── sources_1
└── bd
└── design_1
├── design_1.bd
├── design_1.bxml
├── design_1_ooc.xdc
├── hdl
│ └── design_1_wrapper.v
├── ip
│ └── design_1_processing_system7_0_0
│ ├── design_1_processing_system7_0_0.xci
│ └── design_1_processing_system7_0_0.xml
├── sim
│ └── design_1.v
├── synth
│ └── design_1.v
└── ui
└── bd_1f5defd0.ui
==== Generate block design ====
Majority of output under ''zedboard.ip_user_files/''.
==== Run synthesis ====
==== Run implementation ====
==== Generate bitstream ====
''zedboard.runs/impl_1/design_1_wrapper.bit''
==== Export hardware (include bitstream?) ====
End result:
$ unzip -l design_1_wrapper.hdf
Archive: design_1_wrapper.hdf
02LvEiD+u+Kz8iWSDr/wPVMUtQtx/Up+iy67Wzp7LsT7w=
Length Date Time Name
--------- ---------- ----- ----
861 05-20-2019 07:27 hwdef.xml
66717 05-20-2019 07:27 design_1.hwh
6451 05-20-2019 07:27 design_1_bd.tcl
313654 05-20-2019 07:27 ps7_init.c
4908 05-20-2019 07:27 ps7_init.h
313050 05-20-2019 07:27 ps7_init_gpl.c
4294 05-20-2019 07:27 ps7_init_gpl.h
1760914 05-20-2019 07:27 ps7_init.html
24922 05-20-2019 07:27 ps7_init.tcl
--------- -------
2495771 9 files
$
===== PetaLinux steps =====
==== petalinux-create ====
$ petalinux-create \
--type project \
--name zed \
--template zynq
$ cd zed
$
Output:
.
├── config.project
└── project-spec
├── attributes
├── configs
│ ├── config
│ └── rootfs_config
├── hw-description
│ └── metadata
└── meta-user
├── conf
│ ├── layer.conf
│ └── petalinuxbsp.conf
├── COPYING.MIT
├── README
├── recipes-apps
│ ├── gpio-demo
│ │ ├── files
│ │ │ ├── gpio-demo.c
│ │ │ └── Makefile
│ │ └── gpio-demo.bb
│ └── peekpoke
│ ├── files
│ │ ├── Makefile
│ │ ├── peek.c
│ │ └── poke.c
│ └── peekpoke.bb
├── recipes-bsp
│ ├── device-tree
│ │ ├── device-tree.bbappend
│ │ └── files
│ │ └── system-user.dtsi
│ └── u-boot
│ ├── files
│ │ └── platform-top.h
│ └── u-boot-xlnx_%.bbappend
└── recipes-core
└── images
└── petalinux-image-full.bbappend
==== petalinux-config ====
$ petalinux-config --get-hw-description
==== petalinux-build ====