risc-v

Differences

This shows you the differences between two versions of the page.

Link to this comparison view

Both sides previous revision Previous revision
Next revision		 Previous revision
risc-v [2022/02/28 10:31] – [Generated image/boot/ artifacts] rpjdayrisc-v [2022/03/01 14:09] (current) – [meta-riscv layer [abbreviated]] rpjday
Line 27: Line 27:
         * [[https://git.openembedded.org/openembedded-core/tree/meta/recipes-bsp/opensbi/opensbi_1.0.bb|opensbi_1.0.bb]]         * [[https://git.openembedded.org/openembedded-core/tree/meta/recipes-bsp/opensbi/opensbi_1.0.bb|opensbi_1.0.bb]]
         * [[https://git.openembedded.org/openembedded-core/tree/meta/recipes-bsp/opensbi/opensbi-payloads.inc|opensbi-payloads.inc]]         * [[https://git.openembedded.org/openembedded-core/tree/meta/recipes-bsp/opensbi/opensbi-payloads.inc|opensbi-payloads.inc]]
 +      * [[https://git.openembedded.org/openembedded-core/tree/meta/recipes-bsp/u-boot|u-boot/]]
 +        * [[https://git.openembedded.org/openembedded-core/tree/meta/recipes-bsp/u-boot/u-boot-common.inc|u-boot-common.inc]]
 +        * [[https://cgit.openembedded.org/openembedded-core/tree/meta/recipes-bsp/u-boot/u-boot.inc|u-boot.inc]]
 +        * [[https://cgit.openembedded.org/openembedded-core/tree/meta/recipes-bsp/u-boot/u-boot_2022.01.bb|u-boot_2022.01.bb]]
  
  
-== meta-riscv layer [abbreviated]+== meta-riscv layer [abbreviated, unnecessary for QEMU]
  
   * [[https://github.com/riscv/meta-riscv|meta-riscv/]]   * [[https://github.com/riscv/meta-riscv|meta-riscv/]]
Line 37: Line 41:
     * [[https://github.com/riscv/meta-riscv/tree/master/recipes-bsp/u-boot|U-Boot stuff]]     * [[https://github.com/riscv/meta-riscv/tree/master/recipes-bsp/u-boot|U-Boot stuff]]
     * [[https://github.com/riscv/meta-riscv/tree/master/recipes-kernel/|recipes-kernel/]]     * [[https://github.com/riscv/meta-riscv/tree/master/recipes-kernel/|recipes-kernel/]]
-      * [[https://github.com/riscv/meta-riscv/tree/master/recipes-kernel/firmware|firmware/]] 
       * [[https://github.com/riscv/meta-riscv/tree/master/recipes-kernel/linux|linux/]]       * [[https://github.com/riscv/meta-riscv/tree/master/recipes-kernel/linux|linux/]]
  
Line 88: Line 91:
 </code> </code>
  
-Why create a kernel containing-payload if you don't use it?+Why create a kernel containing-payload if you don't use it? Also, appears that the serial console is ''ttyS0'', and you can drop the ''console=hvc0 earlycon=sbi'' stuff, still works.
  
 == tmp/deploy/images/qemuriscv64 == tmp/deploy/images/qemuriscv64
Line 137: Line 140:
 == linux-yocto_5.15.bb == linux-yocto_5.15.bb
  
-Carefully selected snippets:+Snippets:
  
 <code> <code>
Line 145: Line 148:
 SRC_URI = "git://git.yoctoproject.org/linux-yocto.git;name=machine;branch=${KBRANCH}; \ SRC_URI = "git://git.yoctoproject.org/linux-yocto.git;name=machine;branch=${KBRANCH}; \
            git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-5.15;destsuffix=${KMETA}"            git://git.yoctoproject.org/yocto-kernel-cache;type=kmeta;name=meta;branch=yocto-5.15;destsuffix=${KMETA}"
 +           
 + # Functionality flags
 +KERNEL_EXTRA_FEATURES ?= "features/netfilter/netfilter.scc"
 +KERNEL_FEATURES:append = " ${KERNEL_EXTRA_FEATURES}"
 +KERNEL_FEATURES:append:qemuall=" cfg/virtio.scc features/drm-bochs/drm-bochs.scc"          
 </code> </code>
 == Generated RISC-V image/boot/ artifacts == Generated RISC-V image/boot/ artifacts
Line 249: Line 257:
 </code> </code>
  
 +== On the running QEMU session
 +
 +<code>
 +root@qemuriscv64:/proc# gunzip -c /proc/config.gz | grep RISC
 +CONFIG_RISCV=y
 +CONFIG_RISCV_SBI=y
 +CONFIG_RISCV_ERRATA_ALTERNATIVE=y
 +CONFIG_RISCV_ISA_C=y
 +CONFIG_RISCV_BASE_PMU=y
 +CONFIG_RISCV_SBI_V01=y
 +# CONFIG_SERIAL_EARLYCON_RISCV_SBI is not set
 +# CONFIG_HVC_RISCV_SBI is not set
 +CONFIG_RISCV_TIMER=y
 +CONFIG_RISCV_INTC=y
 +</code>
 = opensbi = opensbi
  
Line 257: Line 280:
 RISCV_SBI_PLAT ?= "generic" RISCV_SBI_PLAT ?= "generic"
 RISCV_SBI_PAYLOAD ?= "${KERNEL_IMAGETYPE}-${MACHINE}.bin" RISCV_SBI_PAYLOAD ?= "${KERNEL_IMAGETYPE}-${MACHINE}.bin"
 +
 +UBOOT_ENTRYPOINT:riscv32 = "0x80400000"
 +UBOOT_ENTRYPOINT:riscv64 = "0x80200000"
 </code> </code>
  
Line 303: Line 329:
  
 <code> <code>
 +require opensbi-payloads.inc
 +
 +inherit autotools-brokensep deploy
 +
 +SRCREV = "ce4c0188d96b2c20c2e08d24646a5e517fe15a4b"
 +SRC_URI = "git://github.com/riscv/opensbi.git;branch=master;protocol=https \
 +          "
 +
 +S = "${WORKDIR}/git"
 +
 EXTRA_OEMAKE += "PLATFORM=${RISCV_SBI_PLAT} I=${D} FW_PIC=n CLANG_TARGET= " EXTRA_OEMAKE += "PLATFORM=${RISCV_SBI_PLAT} I=${D} FW_PIC=n CLANG_TARGET= "
 # If RISCV_SBI_PAYLOAD is set then include it as a payload # If RISCV_SBI_PAYLOAD is set then include it as a payload
Line 330: Line 366:
 FILES:${PN} += "/share/opensbi/*/${RISCV_SBI_PLAT}/firmware/fw_payload.*" FILES:${PN} += "/share/opensbi/*/${RISCV_SBI_PLAT}/firmware/fw_payload.*"
 FILES:${PN} += "/share/opensbi/*/${RISCV_SBI_PLAT}/firmware/fw_dynamic.*" FILES:${PN} += "/share/opensbi/*/${RISCV_SBI_PLAT}/firmware/fw_dynamic.*"
-</code> 
  
 +COMPATIBLE_HOST = "(riscv64|riscv32).*"
 +INHIBIT_PACKAGE_STRIP = "1"
 +
 +SECURITY_CFLAGS = ""
 +</code>
 == bitbake -e opensbi == bitbake -e opensbi
  
Line 347: Line 387:
  
 == git/build/platform/generic/firmware == git/build/platform/generic/firmware
 +
 +With (default) kernel payload:
  
 <code> <code>
Line 355: Line 397:
 -rwxr-xr-x. 1 rpjday rpjday 24799752 Feb 27 05:28 fw_payload.bin -rwxr-xr-x. 1 rpjday rpjday 24799752 Feb 27 05:28 fw_payload.bin
 -rwxr-xr-x. 1 rpjday rpjday 23640912 Feb 27 05:28 fw_payload.elf -rwxr-xr-x. 1 rpjday rpjday 23640912 Feb 27 05:28 fw_payload.elf
 +</code>
 +
 +With ''u-boot.bin'' payload (note much smaller payload files):
 +
 +<code>
 +-rwxr-xr-x. 2 rpjday rpjday   96496 Mar  1 06:10 fw_dynamic.bin
 +-rwxr-xr-x. 2 rpjday rpjday  938520 Mar  1 06:10 fw_dynamic.elf
 +-rwxr-xr-x. 2 rpjday rpjday   96496 Mar  1 06:10 fw_jump.bin
 +-rwxr-xr-x. 2 rpjday rpjday  938104 Mar  1 06:10 fw_jump.elf
 +-rwxr-xr-x. 2 rpjday rpjday 2713192 Mar  1 06:10 fw_payload.bin
 +-rwxr-xr-x. 2 rpjday rpjday 1554336 Mar  1 06:10 fw_payload.elf
 </code> </code>
  
  • risc-v.1646044281.txt.gz
  • Last modified: 2022/02/28 10:31
  • by rpjday