Differences
This shows you the differences between two versions of the page.
| Both sides previous revision Previous revision Next revision | Previous revision | ||
| phy [2018/10/08 12:12] – [PCS (Physical Coding Sublayer)] rpjday | phy [2018/10/08 12:59] (current) – [Overview] rpjday | ||
|---|---|---|---|
| Line 5: | Line 5: | ||
| * Data link layer | * Data link layer | ||
| * LLC | * LLC | ||
| - | * MAC | + | * MAC (FLGA core) |
| * Reconciliation | * Reconciliation | ||
| - | * PHY | + | * PHY (FPGA core) |
| * PCS (Physical Coding Sublayer) | * PCS (Physical Coding Sublayer) | ||
| * PMA (Physical Medium Attachment) | * PMA (Physical Medium Attachment) | ||
| * PMD (Physical Medium Dependent) | * PMD (Physical Medium Dependent) | ||
| + | * [AUTONEG] | ||
| * MDI (Medium Dependent Interface) | * MDI (Medium Dependent Interface) | ||
| * Medium | * Medium | ||
| Line 40: | Line 41: | ||
| * IEEE 1588 (PTP) support | * IEEE 1588 (PTP) support | ||
| * support for options not strictly in conformance of the 10GbE spec such as shrinking the Ethernet preamble and/or interpacket gap to reduce latency between MAC and PHYs offering this support | * support for options not strictly in conformance of the 10GbE spec such as shrinking the Ethernet preamble and/or interpacket gap to reduce latency between MAC and PHYs offering this support | ||
| + | |||
| + | ===== Layer generalization ===== | ||
| + | |||
| + | |||
| + | * Physical: The physical medium is quite likely to either be a fibre patchcord or a twinaxial copper cable. | ||
| + | * PMD: This is plugged into a transceiver which implements the PMD, converting whatever physical medium is used; light or electrons, into a stream of electrons matching a defined interface talking to the PMA. | ||
| + | * PMA: The PMA is part of an FPGA chip and does a number of things. It works out where each bit begins and ends in the stream and recovers the clock from the stream. It then deserialises the incoming stream at 10.3125 Gbps into typically a 32 or 64 bit bus clocked at ~322 Mhz or ~161 Mhz which is passed to the PCS. | ||
| + | * PCS: The PCS first synchronises with the stream by identifying special symbols sent periodically in the stream to indicate the start of a line-encoded block. It then descrambles the blocks which have been scrambled using a polynomial scrambler designed to prevent DC bias (too many zeros or ones in succession that would cause a loss of lock by the PMA and PCS or too many ones in succession that would cause bit errors) and passes the descrambled stream to the MAC. Some models of FPGA have hard IP implementations of this layer. | ||
| + | * MAC: The MAC converts the decoded stream into Ethernet frames which it passes to the FPGA application. It also flags errors in the stream and maintains statistics. A PTP-aware MAC also timestamps Ethernet frames for PTP clock synchronisation | ||
| ===== Layers ===== | ===== Layers ===== | ||
| Line 59: | Line 69: | ||
| * PCS/PMA management registers with optional MDIO interface | * PCS/PMA management registers with optional MDIO interface | ||
| + | "This sublayer determines when a functional link has been established, | ||
| ==== PMA (Physical Medium Attachment) ==== | ==== PMA (Physical Medium Attachment) ==== | ||
| ==== PMD (Physical Medium Dependent (sublayer) ==== | ==== PMD (Physical Medium Dependent (sublayer) ==== | ||